1. Field of the Invention
The present invention relates to a flash memory and a method for manufacturing the same.
2. Description of the Related Art
A semiconductor memory may be classified as a volatile memory or a non-volatile memory. In an aspect of process technology, a non-volatile memory device may be classified as a floating gate memory device or a metal insulator semiconductor (MIS) memory device having more than two dielectric layers that are doubly or triply stacked.
The floating gate memory device embodies a memory character by using a potential well, and includes an erasable programmable read only memory (EPROM) tunnel oxide (ETOX) in a simple stacked structure that is widely used in an electrically erasable programmable read only memory (EEPROM), and/or a split gate structure that includes two transistors in one cell.
On the other hand, the MIS memory device performs memory functions by using a charge trapping layer that may occur in a dielectric layer bulk, a dielectric layer-dielectric layer interface, and/or a dielectric layer-semiconductor interface. An example of such a MIS memory is a metal/silicon oxide-nitride-oxide (ONO) semiconductor (MONOS/SONOS) structure that is widely applied to a flash EEPROM.
A related art flash memory unit cell is described with reference to FIG. 1.
A gate oxide layer 12 is formed on a semiconductor substrate 10 having a device isolation layer 11. A first poly silicon layer is formed on the gate oxide layer 12 to be used as a floating gate 13. A dielectric layer 15 and a second poly silicon layer are formed on the floating gate 13. The second poly silicon layer is used as a control gate 16. The dielectric layer 15 may include an ONO layer. A metal layer 17 and a nitride layer 18 are formed on the top of the control gate 16, and are then patterned in a cell structure to form a flash memory cell 90.
The flash memory device includes a source connection layer connecting sources in each unit cell to form a source line. In a recent flash memory device, the source connection layer mainly uses a source line comprising an impurity diffusion layer to achieve a high degree of integration by a self aligned source (SAS) process.
Hereinafter, a flash memory 100 made using a SAS process is described with reference to FIGS. 2 to 5.
FIG. 2 is a plan view of the related art flash memory 100.
Here, a reference number 50 is a gate extending along a word line WL direction on the semiconductor substrate. A reference number 11 represents a device isolation region formed by a shallow trench isolation (STI) process. At this point, a dotted line is a boundary of an inclined plane in a sidewall of the trench isolation. A reference number 20 is a source line doped with an impurity in a memory cell made by a SAS process.
In the SAS process, after opening a source region of a cell using an additional SAS mask when a gate electrode in a stacked structure is formed, an anisotropic etching process is performed to remove a device isolation region 11 (generally, a field oxide layer) where a source line will be formed for a common source line in adjacent cells.
The source line of the flash memory using a SAS process will described in more detail with reference to FIGS. 3 to 5.
FIG. 3 is sectional view taken along line A-A′ in an active region of a semiconductor substrate of FIG. 2. Two stacked gates 50 and a common source line 20 will be mainly described for convenience.
A first stacked gate 50 includes a gate oxide layer 12 on a semiconductor substrate 10, a floating gate 13 on the gate oxide layer 12, an ONO dielectric layer 15 on the floating gate 13, and a control gate 16. A second stacked gate 50 has a structure identical to that of the first stacked gate 50. A source line 20 is formed between the first stacked gate 50 and the second stacked gate 50.
A method for manufacturing the source line 20 by using a related art SAS process includes etching an oxide layer, i.e., a device isolation layer 11 (see FIG. 4) in a field region after forming the stacked gate 50, and performing an ion implantation process to form a low resistance source line 20. In this case, an interval between the source line 20 and the stacked gate 50 largely disappears according to a SAS technology characteristic.
FIG. 4 is a sectional view taken along line B-B′ in the device isolation region of the semiconductor substrate in FIG. 2. Unlike FIG. 3, which does not include a field region, the device isolation layer 11 in a portion of the substrate 10 where a common source line is formed is removed to form a source line 20.
FIG. 5 is a sectional view taken along line C-C′ in the source line 20 of FIG. 2. This illustrates the entire source line 20.
A related art method for manufacturing the source line 20 includes forming a stacked gate, and then performing an ion implantation after etching an oxide layer (i.e., a device isolation layer 11 in a field region of the device) using a photoresist mask. During the etching of the oxide layer, the top portion of the stacked gate 50 may be removed.
Additionally, when an angle is out of range during an ion implantation, a fatal damage may occur in the stacked gate 50, thereby deteriorating reliability of the semiconductor device. When reliability deteriorates in a semiconductor device, operations in manufacturing the semiconductor device may increase in number, and thus the costs of semiconductor manufacturing may increase.
Furthermore, since a common source line is formed along a profile of a trench in a memory cell using a SAS technology, contact resistance of a source in each actual cell may drastically increase. Especially, most memory cells use STI technology as a separation technology when its size is below 0.25 μm or 0.18 μm. The STI technology is necessary to reduce the size of cell in a word line WL direction, and the SAS technology is necessary to reduce the size of cell in a bit line BL direction. When two technologies are applied, a source resistance may drastically increase.
Especially, since the flash memory uses an internal high voltage, as the size of cell decreases and the trench depth deepens, the relative length of the common source line increases. A relatively long source line is disadvantageous for source resistance. In embedded flash memory, programming characteristics and reading speed may deteriorate, thereby adversely affecting product performance over large numbers of devices.